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freescale semiconductor data sheet: technical data document number: mc9s08mp16 rev. 2, 08/2011 ? freescale semiconductor, inc., 2009-2011. all rights reserved. freescale reserves the right to change the deta il specifications as may be required to permit improvements in the design of its products. 48-lqfp case 932-03 28-soic case 751f-05 32-lqfp case 873a-03 features ? 8-bit hcs08 central processor unit (cpu) ? up to 51.34 mhz cpu at 2.7v to 5.5v across temperature range of ?40c to 105c ? up to 40 mhz cpu at 2.7v to 5.5v across temperature range of ?40c to 125c ? hc08 instruction set with added bgnd instruction and additional addressing modes for ldhx and sthx ? support for up to 48 interrupt/reset sources ?on-chip memory ? up to 16 kb flash memory; read/program/e rase over full operating voltage and temperature ? up to 1 kb random-access memory (ram) ? security circuitry to prevent un authorized access to ram and flash memory contents ? power-saving modes ? two low power stop modes; reduced power wait mode ? peripheral clock gating can di sable clocks to unused modules ? clock source options ? oscillator (xosc) ? loop-control pierce oscillator; crystal or ceramic resonator range of 31.25?38.4 khz or 1?16 mhz ? internal clock source (ics) ? containing a frequency-locked-loop (fll) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resoluti ons and 2% deviati on over temperature and voltage; supports cpu frequencies up to 51.34 mhz ? system protection ? watchdog computer operating properly (cop) reset running from dedicated 1-khz internal clock source or bus clock ? low-voltage detection with reset or interrupt; selectable trip points ? illegal opcode and illegal a ddress detection with reset ? flash memory block protection ? development support ? single-wire bac kground debug interface ? breakpoint capability to allo w single breakpoint setting during in-circuit debugging (plus three more breakpoints in on-chip debug module) ? on-chip in-circuit emulator (ice) debug module containing three comparators and nine trigge r modes. eight deep fifo for storing change-of-flow addresses and event-only data. debug module supports both tag and force breakpoints ? peripherals ? ipc ? interrupt priority cont roller with 4 programmable interrupt priority levels ? adc ? 13-channel, 12-bit resolution; 2.5 ? s conversion time; automatic compare function; 1.7 mv/ ? c temperature sensor; internal bandgap re ference channel; operation in stop3 ? pga ? differential programmable gain amplifier with programmable gain (x1, x2, x4, x8, x16, or x32) ? hscmp ? three fast analog compar ators with positive and negative inputs; separately sele ctable interrupt on rising and falling comparator output; filt ering; windowing; hscmp1 and hscmp2 outputs can be optionall y routed to ftm1 module; runs in stop3 ? dac ? three 5-bit digital to analog convertor used as a 32-tap voltage reference for each comparator ? pdb ? two programmable delay blocks: pdb1 synchronizes pwm with samples of adc; pdb2 synchronizes pwm with comparing window of analog comparators ? sci ? full duplex non-return to zero (nrz); lin master extended break generation; lin slave extended break detection; wake up on active edge ? spi ? full-duplex or single- wire bidire ctional; double-buffered transmit and re ceive; master or slave mode; msb-first or lsb-first shifting ? iic/smbus ? up to 400 kbps; multi-master operation; programmable slave address; interrupt driven byte-by-byte data transfer; supports broadcast mode and 10-bit addressing; smbus compatible ? ftm ? two flextimers with total of 8 channels; one 2-channel (ftm1) and one 6-channel (ftm2); supports operation up to 2x bus clock; se lectable input capture, output compare, edge- or center-aligne d pwm; dead time insertion; fault inputs ? mtim ? 8-bit modulo counter with 8-bit prescaler ? rtc ? (real-time counter) 8- bit modulus counter with binary or decimal based prescale r; external clock source for precise time base, time-of-day, calendar or task scheduling; free running on-chip low power oscillator (1 khz) for cyclic wake-up without external compone nts, runs in all mcu modes ? crc ? cyclic redundancy check generator ? kbi ? three 8 channel keyboard interrupt module with software selectable polarity on edge or edge/level modes ? input/output ? 40 gpios, 2 output-only pins. ? hysteresis and configurable pull up device on input pins; configurable slew rate and drive strength on output pins; sink/source current up to 20ma ? package options ? 48-lqfp, 32-lqfp, 28-soic ? 48-lqfp qualified for automotive usage mc9s08mp16 series data sheet
mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 2 table of contents 1 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . .9 2.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .9 2.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .10 2.5 esd protection and latch-up immunity . . . . . . . . . . . .11 2.6 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.7 supply current characteristics . . . . . . . . . . . . . . . . . . .15 2.8 external oscillator (xosc) characteristics . . . . . . . . .20 2.9 internal clock source (ics) characteristics . . . . . . . . .21 2.10 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.11 digital to analog (dac) characteristics . . . . . . . . . . . .26 2.12 high speed comparator (hscmp) characteristics . . .26 2.13 programmable gain amplifier (pga) characteristics . 26 2.14 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.14.1 control timing . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.14.2 ftm module timing . . . . . . . . . . . . . . . . . . . . . 28 2.14.3 mtim module timing . . . . . . . . . . . . . . . . . . . . 29 2.14.4 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.15 flash memory specifications. . . . . . . . . . . . . . . . . . . . 33 2.16 emc performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.16.1 radiated emissions . . . . . . . . . . . . . . . . . . . . . 33 3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1 device numbering scheme. . . . . . . . . . . . . . . . . . . . . 35 4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5 related documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 3 figure 1. mc9s08mp16 series block diagram 8-bit keyboard interrupt ( kbi1 ) iic module ( iic ) serial peripheral interface ( spi ) user ram on-chip ice debug module ( dbg ) hcs08 core cpu bkgd int bkp 6-channel flextimer ( ftm2 ) hcs08 system control resets and interrupts modes of operation power management cop lv d serial communications voltage regulator user flash interface ( sci ) txd rxd ss spsck scl sda mosi miso v ssa /v refl v dda /v refh xtal extal kbi1p[7:0] reset ftm1ch[1:0] analog-to-digital converter ( adc ) 12-bit high speed analog comparator ( hscmp1 ) pga? pga+ cyclic redundancy check ( crc ) tclk ftm1fault ftm2ch[5:0] tclk notes: when ptf1 is configured as reset , pin becomes bi-directional with output being open-drain drive containing an internal pull-up device. when ptf0 is configured as bkgd, pin becomes bi-directional. cmp1out bkgd/ms 8-bit modulo timer ( mtim ) tclk digital-to-analog converter ( dac2 ) v refl v refh adp12?adp0 port a pta1/scl/rxd pta3/scl/ftm1ch1 pta2/sda/ftm1ch0 pta0/sda/txd pta4/tclk/sda/ss pta5/scl/miso pta7/spsck pta6/mosi gain amplifier ( pga ) programmable 8-bit keyboard interrupt ( kbi2 ) kbi2p[7:0] port b ptb1/kbi1p1/adp1/c2in2 ptb3/kbi1p3/adp3/c3in2/pga- ptb2/kbi1p2/adp2/c1in2/pga+ ptb0/kbi1p0/adp0/cin1 ptb4/kbi1p4/adp4/c2in3 ptb5/kbi1p5/cmp2out/adp5/c2in4 ptb7/kbi1p7/adp7/c3in4 ptb6/kbi1p6/cmp3out/adp6/c3in3 ftm2fault port c ptc1/kbi2p1/ftm2ch1 ptc3/kbi2p3/ftm2ch3 ptc2/kbi2p2/ftm2ch2 ptc0/kbi2p0/ftm2ch0 ptc4/kbi2p4/ftm2ch4 ptc5/kbi2p5/ftm2ch5 ptc7/kbi2p7/tclk ptc6/kbi2p6/ftm2fault port d ptd1/kbi3p1/scl ptd3/kbi3p3/ftm1fault ptd2/kbi3p2/pdb1out ptd0/kbi3p0/sda ptd4/kbi3p4/pdb2out ptd5/kbi3p5/cmp1out ptd7/kbi3p7/cmp3out ptd6/kbi3p6/cmp2out port e pte1/adp9 pte3/adp11/c1in3 pte2/adp10 pte0/adp8 pte4/adp12/c1in4 pte5/xtal pte6/extal port f ptf1/reset ptf2 ptf0/bkgd/ms pins not available on 28-pin packages 8-bit keyboard interrupt ( kbi3 ) kbi3p[7:0] cin1 c1in2 c1in3 c1in4 high speed analog comparator ( hscmp2 ) cmp2out c2in2 c2in3 c2in4 high speed analog comparator ( hscmp3 ) cmp3out c3in2 c3in3 c3in4 programmable delay block ( pdb1 ) programmable delay block ( pdb2 ) v dd2 pad is tied internally on 32-pin and 28-pin packages, low-power oscillator 50.33 mhz internal clock source ( ics ) 31.25 khz to 38.4 khz 1 mhz to 16 mhz ( xosc ) real time counter ( rtc ) v ss2 pad is tied internally on 28-pin packages digital-to-analog converter ( dac1 ) digital-to-analog converter ( dac3 ) pdb1out pdb2out v dd1 v ss1 v dd2 v ss2 pins not available on 32-pin or 28-pin packages (mc9s08mp16 = 16384 bytes) (mc9s08mp12 = 12288 bytes) (mc9s08mp16 = 1024 bytes) (mc9s08mp12 = 512 bytes) (only on mc9s08mp16) (only on mc9s08mp16) interrupt priority controller (ipc) 2-channel flextimer ( ftm1 )
mc9s08mp16 series data sheet, rev. 2 pin assignments freescale semiconductor 4 1 pin assignments this section shows the pin assignments for the mc9s08mp16 series devices. figure 2. mc9s08mp16 series in 48-lqfp v dda /v refh ptc6/kbi2p6/ftm2fault ptf0/bkgd/ms pta0/sda/txd ptc5/kbi2p5/ftm2ch5 ptc1/kbi2p1/ftm2ch1 ptc2/kbi2p2/ftm2ch2 ptb2/kbi1p2/adp2/c1in2/pga+ ptb7/kbi1p7/adp7/c3in4 pta5/scl/miso pta6/mosi pta7/spsck ptb0/kbi1p0/adp0/cin1 ptb1/kbi1p1/adp1/c2in2 ptb5/kbi1p5/cmp2out/adp5/c2in4 ptb4/kbi1p4/adp4/c2in3 ptb6/kbi1p6/cmp3out/adp6/c3in3 pta4/tclk/sda/ss v ss1 pte5/xtal pta2/sda/ftm1ch0 v ss2 ptc7/kbi2p7/tclk v dd1 ptc4/kbi2p4/ftm2ch4 ptc3/kbi2p3/ftm2ch3 pta1/scl/rxd v ssa /v refl ptb3/kbi1p3/adp3/c3in2/pga? pte6/extal pte1/adp9 pte2/adp10 pte0/adp8 ptf2 ptd4/kbi3p4/pdb2out ptd5/kbi3p5/cmp1out ptd6/kbi3p6/cmp2out ptd7/kbi3p7/cmp3out ptf1/reset pta3/scl/ftm1ch1 ptd3/kbi3p3/ftm1fault ptd2/kbi3p2/pdb1out ptd0/kbi3p0/sda ptd1/kbi3p1/scl v dd2 pte4/adp12/c1in4 pte3/adp11/c1in3 ptc0/kbi2p0/ftm2ch0 note: pins in bold are lost in the next lower pin count package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37
pin assignments mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 5 figure 3. mc9s08mp16 series in 32-pin lqfp package v dda /v refh ptc6/kbi2p6/ftm2fault ptf0/bkgd/ms pta0/sda/txd ptc5/kbi2p5/ftm2ch5 ptc1/kbi2p1/ftm2ch1 ptc2/kbi2p2/ftm2ch2 ptb2/kbi1p2/adp2/c1in2/pga+ ptb7/kbi1p7/adp7/c3in4 pta5/scl/miso pta6/mosi pta7/spsck ptb0/kbi1p0/adp0/cin1 ptb1/kbi1p1/adp1/c2in2 ptb5/kbi1p5/cmp2out/adp5/c2in4 ptb4/kbi1p4/adp4/c2in3 ptb6/kbi1p6/cmp3out/adp6/c3in3 pta4/tcl:k/sda/ss ptf1/reset v ss1 pte5/xtal pta2/sda/ftm1ch0 pta3/scl/ftm1ch1 v ss2 ptc0/kbi2p0/ftm2ch0 v dd1 ptc4/kbi2p4/ftm2ch4 ptc3/kbi2p3/ftm2ch3 pta1/scl/rxd v ssa /v refl ptb3/kbi1p3/adp3/c3in2/pga? pte6/extal note: pins in bold are lost in the next lower pin count package. 1 2 3 4 5 6 7 8 19 18 17 10 11 12 13 14 15 9 24 32 16 25 26 27 20 21 22 23 31 30 29 28
mc9s08mp16 series data sheet, rev. 2 pin assignments freescale semiconductor 6 figure 4. mc9s08mp16 series in 28-pin soic package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ptc1/kbi2p1/ftm2ch1 ptc2/kbi2p2/ftm2ch2 ptb6/kbi1p6/cmp3out/adp6/c3in3 ptc0/kbi2p0/ftm2ch0 ptc6/kbi2p6/ftm2fault ptf0/bkgd/ms pta0/sda/txd ptc5/kbi2p5/ftm2ch5 pta2/sda/ftm1ch0 ptc4/kbi2p4/ftm2ch4 ptc3/kbi2p3/ftm2ch3 pta1/scl/rxd pta5/scl/miso pta6/mosi pta7/spsck pta4/tclk/sda/ss ptf1/reset v ss1 pta3/scl/ftm1ch1 v dd1 v dda /v refh ptb2/kbi1p2/adp2/c1in2/pga+ ptb0/kbi1p0/adp0/cin1 ptb1/kbi1p1/adp1/c2in2 ptb5/kbi1p5/cmp2out/adp5/c2in4 ptb4/kbi1p4/adp4/c2in3 v ssa /v refl ptb3/kbi1p3/adp3/c3in2/pga?
pin assignments mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 7 table 1. pin availability by package pin-count pin number <-- lowest priority --> highest 48 32 lqfp 28 port pin alt 1 alt 2 alt3 alt4 1 3 5 ptc4 kbi2p4 ftm2ch4 2 4 6 ptc5 kbi2p5 ftm2ch5 3 5 7 ptc6 kbi2p6 ftm2fault 4 ?? ptc7 kbi2p7 tclk 1 5 ?? ptd0 kbi3p0 sda 5 6 ?? ptd1 kbi3p1 scl 5 7 ?? ptd2 kbi3p2 pdb1out 8 ?? ptd3 kbi3p3 ftm1fault 968 v ss1 10 7 9 v dd1 11810pta0sda 5 txd 12911pta1scl 5 rxd 13 10 12 pta2 sda 5 ftm1ch0 14 11 13 pta3 scl 5 ftm1ch1 15 ?? ptd4 kbi3p4 pdb2out 16 ?? ptd5 kbi3p5 cmp1out 17 ?? ptd6 kbi3p6 cmp2out 2 18 ?? ptd7 kbi3p7 cmp3out 3 19 12 14 ptf1 reset 4 20 ?? ptf2 21 13 15 pta4 tclk 1 sda 5 ss 22 14 16 pta5 scl 5 miso 23 15 17 pta6 mosi 24 16 18 pta7 spsck 25 ?? pte0 adp8 26 ?? pte1 adp9 27 ?? pte2 adp10 28 17 19 ptb0 kbi1p0 adp0 6 cin1 6 29 18 20 ptb1 kbi1p1 adp1 6 c2in2 6 30 19 21 ptb2 kbi1p2 adp2 6 c1in2 6 pga+ 6 31 20 22 ptb3 kbi1p3 adp3 6 c3in2 6 pga? 6 32 21 23 v dda /v refh 33 22 24 v ssa /v refl 34 ?? pte3 adp11 6 c1in3 6
mc9s08mp16 series data sheet, rev. 2 electrical characteristics freescale semiconductor 8 2 electrical characteristics 2.1 introduction this section contains electrical and timing specifications for the mc9s08mp16 seri es of microcontrollers available at the time of publication. 35 ?? pte4 adp12 6 c1in4 6 36 23 25 ptb4 kbi1p4 adp4 6 c2in3 6 37 24 26 ptb5 kbi1p5 cmp2out 2 adp5 6 c2in4 6 38 25 27 ptb6 kbi1p6 cmp3out 3 adp6 6 c3in3 6 39 26 ? ptb7 kbi1p7 adp7 6 c3in4 6 40 27 ? pte5 xtal 41 28 ? pte6 extal 42 29 ? v ss2 43 ?? v dd2 44 30 28 ptf0 bkgd ms 45 31 1 ptc0 kbi2p0 ftm2ch0 46 32 2 ptc1 kbi2p1 ftm2ch1 47 1 3 ptc2 kbi2p2 ftm2ch2 48 2 4 ptc3 kbi2p3 ftm2ch3 1 tclk pin can be repositioned using tclkps in sopt2. defa ult reset location is ptc7. 2 hscmp2 output cmp2out can be repositioned using the cmp2ops in the sopt2 register. default reset location is ptd6. 3 hscmp3 output cmp3out can be repositioned using the cmp3ops in the sopt2 register. default reset location is ptd7. 4 pin is open drain with an internal pullup that is always enabled. pin does not contain a clamp diode to v dd and should not be driven above v dd . the voltage measured on the internally pulled up reset will not be pulled to v dd . the internal gates connected to this pin are pulled to v dd . 5 iic pins sda and scl can be repositioned using iicps in sopt2. default reset locations are ptd0 and ptd1. 6 if adc, hscmp, or pga is enabling a shared analog input pin, each has access to the pin. table 1. pin availability by package pin-count (continued) pin number <-- lowest priority --> highest 48 32 lqfp 28 port pin alt 1 alt 2 alt3 alt4
electrical characteristics mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 9 2.2 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following cla ssification is used and the parameters are tagge d accordingly in the tables where appropriate: note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 2.3 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits specified in table 3 may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this section. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advise d that normal precautions be taken to av oid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs ar e tied to an appropriate logic voltage level (f or instance, either v ss or v dd ) or the programmable pull-up resistor associated with the pin is enabled. table 2. parameter classifications p those parameters that are guaranteed during pro duction testing on each individual device. c those parameters that are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters that are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters that are derived mainly from simulations. table 3. absolute maximum ratings rating symbol value unit supply voltage v dd ?0.3 to +5.8 v maximum current into v dd i dd 120 ma digital input voltage v in ?0.3 to v dd +0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1, 2, 3 1 input must be current limited to the value s pecified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins, except for ptf1/reset are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). i d ? 25 ma storage temperature range t stg ?55 to 150 ? c
mc9s08mp16 series data sheet, rev. 2 electrical characteristics freescale semiconductor 10 2.4 thermal characteristics this section provides information about ope rating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being c ontrolled by the mcu design. to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current fo r each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. the average chip-junction temperature (t j ) in ? c can be obtained from: t j = t a + (p d ? ? ja ) eqn. 1 where: t a = ambient temperature, ? c ? ja = package thermal resist ance, junction-to-ambient, ? c/w p d = p int ?? p i/o p int = i dd ? v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications, p i/o ?? p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k ? (t j + 273 ? c) eqn. 2 solving equation 1 and equation 2 for k gives: k = p d ? (t a + 273 ? c) + ? ja ? (p d ) 2 eqn. 3 table 4. thermal characteristics num c rating symbol consumer & industrial automotive unit 1 ? operating temperature range (packaged) t a ?40 to 105 ?40 to 125 ? c 2 d maximum junction temperature t j 115 135 ? c 3 d thermal resistance 1,2 single-layer board 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipa tion of other components on the board, and board thermal resistance. 2 junction-to-ambient natural convection 48-pin lqfp ? ja 80 80 ? c/w 32-pin lqfp 85 ? 28-pin soic 71 ? 4 d thermal resistance 1,2 four-layer board 48-pin lqfp ? ja 56 56 ? c/w 32-pin lqfp 57 ? 28-pin soic 48 ?
electrical characteristics mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 11 where k is a constant pertaining to the particular pa rt. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation 1 and equation 2 iteratively for any value of t a . 2.5 esd protection and latch-up immunity although damage from electrostatic discharge (esd) is much less common on these devices th an on early cmos circuits, normal handling precautions should be taken to avoid exposure to st atic discharge. qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd testing is in conformity with aec-q100 stress test qu alification for automotive grade integrated circuits. during the device qualification, esd stresses were performed for th e human body model (hbm) and the charge device model (cdm). a device is defined as a failure if after exposure to esd puls es the device no longer meets the device specification. complete dc parametric and functional testing is pe rformed per the applicable device specificat ion at room temperature followed by hot temperature, unless instructed ot herwise in the device specification. 2.6 dc characteristics this section includes informatio n about power supply requiremen ts and i/o pin characteristics. table 5. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ? storage capacitance c 100 pf number of pulses per pin ? 3 latch-up minimum input voltage limit ? 2.5 v maximum input voltage limit 7.5 v table 6. esd and latch-up protection characteristics no. rating 1 1 parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. symbol min max unit 1 human body model (hbm) v hbm ?? 2000 ? v 2 charge device model (cdm) v cdm ?? 500 ? v 3 latch-up current at t a = 125 ? ci lat ?? 100 ? ma table 7. dc characteristics num c characteristic symbol condition min typ 1 max unit 1 ? operating voltage v dd 2.7 ? 5.5 v 2 ? analog supply voltage delta to v dd (v dd ?v dda ) (2) ? v dda ?0 ? 100 mv 3 ? analog ground voltage delta to v ss (v ss ?v ssa ) (2) ? v ssa ?0 ? 100 mv
mc9s08mp16 series data sheet, rev. 2 electrical characteristics freescale semiconductor 12 4 c all i/o pins (except ptf1/reset )5 v, i load = ?4 ma v dd ? 1.5 ? ? p low-drive strength 5 v, i load = ?2 ma v dd ? 0.8 ? ? c output high v oh 3 v, i load = ?1 ma v dd ? 0.8 ? ? v c voltage 5 v, i load = ?20 ma v dd ? 1.5 ? ? p high-drive strength 5 v, i load = ?10 ma v dd ? 0.8 ? ? c3 v, i load = ?5 ma v dd ? 0.8 ? ? 5 d output high current max total i oh for all ports i oht v out < v dd 0 ? ?100 ma 6 c all i/o pins 5 v, i load = 4 ma ? ? 1.5 p (except ptf1/reset )5 v, i load = 2 ma ? ? 0.8 c low-drive strength v ol 3 v, i load = 1 ma ? ? 0.8 v c all i/o pins 5 v, i load = 20 ma ? ? 1.5 p output low (e xcept ptf1/reset )5 v, i load = 10 ma ? ? 0.8 c voltage high-drive strength 3 v, i load = 5 ma ? ? 0.8 7 c ptf1/reset 5 v, i load = 3.2 ma ? ? 1.5 8p 5 v, i load = 1.6 ma ? ? 0.8 9c 3 v, i load = 0.8 ma ? ? 0.8 10 d output low current max total i ol for all ports i olt v out > v ss 0?100ma 11 p input high voltage; all digital inputs v ih 5v 0.65 x v dd ??v c 3v 0.7 x v dd ?? 12 p input low voltage; all digital inputs v il 5v ? ? 0.35 x v dd v c 3v ? ? 0.35 x v dd 13 c input hysteresis v hys 0.06 x v dd v 14 p input leakage current (per pin) ? i in ? v in = v dd or v ss ?? 1 ? a 15 p hi-z (off-state) leakage current (per pin) input/output port pins ? i oz ? v in = v dd or v ss ?? 1 ? a ptf1/reset , pte5/xtal pins v in = v dd or v ss ?? 2 ? a 16 pullup or pulldown 3 resistors; when enabled p i/o pins r pu ,r pd 17 37 52 k ? c ptf1/reset 4 r pu 17 37 52 k ? 17 d dc injection current 5, 6, 7, 8 single pin limit v in > v dd 0?2ma i ic v in < v ss 0 ? ?0.2 ma total mcu limit, includes sum of all stressed pins v in > v dd 0?25ma v in < v ss 0??5ma table 7. dc characteristics (continued) num c characteristic symbol condition min typ 1 max unit
electrical characteristics mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 13 13 c input capacitance, all pins c in ?? 8pf 14 c ram retention voltage v ram ?0.61.0v 15 c por re-arm voltage 9 v por 0.9 1.4 2.0 v 16 d por re-arm time t por 10 ? ? ? s 17 p low-voltage detection threshold ? high range v dd falling v dd rising v lv d 1 3.9 4.0 4.0 4.1 4.1 4.2 v 18 low-voltage detection threshold ? low range v dd falling v dd rising v lv d 0 2.48 2.54 2.56 2.62 2.64 2.70 v p 19 low-voltage warning threshold ? high range 1 v dd falling v dd rising v lvw 3 4.5 4.6 4.6 4.7 4.7 4.8 v p 20 low-voltage warning threshold ? high range 0 v dd falling v dd rising v lvw 2 4.2 4.3 4.3 4.4 4.4 4.5 v p 21 low-voltage warning threshold low range 1 v dd falling v dd rising v lvw 1 2.84 2.90 2.92 2.98 3.00 3.06 v p 22 low-voltage warning threshold ? low range 0 v dd falling v dd rising v lvw 0 2.66 2.72 2.74 2.80 2.82 2.88 v p 23 t low-voltage inhibit reset/recover hysteresis v hys 5 v ? 100 ? mv 3 v ? 60 ? 24 p bandgap voltage reference at 25 ? c 10 v bg 1.18 1.202 1.21 v 25 p bandgap voltage reference across temperature range 10 1.17 ? 1.22 v 1 typical values are measured at 25 ? c. characterized, not tested 2 dc potential difference. 3 when keyboard interrupt is configured to detect rising e dges, pulldown resistors are used in place of pullup resistors. 4 the specified resistor value is the actual value internal to the device. the pullup value may measure higher when measured exte rnally on the pin. 5 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low (which would red uce overall power consumption). 6 input must be current limited to the value specified. to determ ine the value of the required cu rrent-limiting resistor, calcula te resistance values for positive and negative clamp voltag es, then use the larger of the two values. table 7. dc characteristics (continued) num c characteristic symbol condition min typ 1 max unit
mc9s08mp16 series data sheet, rev. 2 electrical characteristics freescale semiconductor 14 figure 5. typical v ol vs i ol , high drive strength (except ptf1/reset) figure 6. typical v ol vs i ol , low drive strength (except ptf1/reset) 7 all functional non-supply pins except ptf1/reset are internally clamped to v ss and v dd . 8 the ptf1/reset pin does not have a clamp diode to v dd . do not drive this pin above v dd . 9 maximum is highest volt age that por is guaranteed. 10 factory trimmed at v dd = 5.0 v v ol (v) i ol (ma) 20 15 10 5 025 0 0.5 1 1.5 2 a) v dd = 5v, high drive v ol (v) i ol (ma) 8 6 4 2 010 0 0.2 0.4 0.8 1.0 b) v dd = 3v, high drive 0.6 125c 25c ?40c max 0.8v@5ma max 1.5v@20ma 125c 25c ?40c v ol (v) i ol (ma) 4 3 2 1 05 0 0.5 1 1.5 2 125c 25c ?40c a) v dd = 5v, low drive v ol (v) i ol (ma) 1.6 1.2 0.8 0.4 02.0 0 0.2 0.4 0.8 1.0 b) v dd = 3v, low drive 0.6 125c 25c ?40c max 0.8v@1ma max 1.5v@4ma
electrical characteristics mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 15 figure 7. typical v dd ? v oh vs i oh , high drive strength figure 8. typical v dd ? v oh vs i oh , low drive strength 2.7 supply current characteristics this section includes information about power supply current in various operating modes. table 8. supply current characteristics num c parameter symbol v dd (v) typ 1 max 2 unit 1 c run supply current 3 measured at (cpu clock = 4 mhz, f bus = 2 mhz) ri dd 52.16 3 ma c31.82.5 2 p run supply current 3 measured at (cpu clock = 16 mhz, f bus = 8 mhz) ri dd 5 5.26 7.5 ma c 3 4.92 7 i oh (ma) ?20 ?15 ?10 ?5 0?25 0 0.5 1 1.5 2 125c 25c ?40c a) v dd = 5v, high drive i oh (ma) ?8 ?6 ?4 ?2 0?10 0 0.2 0.4 0.8 1.0 b) v dd = 3v, high drive 0.6 125c 25c ?40c max 0.8v@ ?5ma max 1.5v@ ?20ma v dd ? v oh (v) v dd ? v oh (v) v dd ? v oh (v) i oh (ma) ?4 ?3 ?2 ?1 0?5 0 0.5 1 1.5 2 125c 25c ?40c a) v dd = 5v, low drive i oh (ma) ?1.6 ?1.2 ?0.8 ?0.4 0 ?2.0 0 0.2 0.4 0.8 1.0 b) v dd = 3v, low drive 0.6 125c 25c ?40c max 0.8v@ ?1ma max 1.5v@ ?4ma v dd ? v oh (v)
mc9s08mp16 series data sheet, rev. 2 electrical characteristics freescale semiconductor 16 3 c run supply current 4 measured at (cpu clock = 32 mhz, f bus = 16 mhz) ri dd 59.4 10 ma c3910 4 p run supply current 5 measured at (cpu clock = 51.34 mhz, f bus = 25.67 mhz) ri dd 514.3 30 ma c 3 13.9 20 5 p run supply current measured at (cpu clock = 40 mhz, f bus = 20 mhz) ri dd 516 30 ma ?3?? 6c wait mode supply current measured at (cpu clock = 8 mhz, f bus = 4 mhz) (fei mode, all modules off) wi dd 52.7 ?ma 7 stop3 mode supply current c?40 ? c s3i dd 5 0.96 ? ? a p25 ? c1.3? c85 ? c7.525 p 6 105 ? c 37 90 p125 ? c 65 150 c?40 ? c 3 0.85 ? ? a p25 ? c1.2? c85 ? c6.520 p 6 105 ? c 32.7 80 p125 ? c 58 130 8 stop2 mode supply current c?40 ? c s2i dd 5 0.94 ? ? a p25 ? c1.25? c85 ? c725 p 6 105 ? c 30 65 p125 ? c 64 120 c?40 ? c 3 0.83 ? ? a p25 ? c1.1? c85 ? c6.320 p 6 105 ? c 25 55 p125 ? c 57 100 9 c rtc adder to stop2 or stop3 7 s23i ddrtc 5 300 500 na 3 300 500 na table 8. supply current characteristics (continued) num c parameter symbol v dd (v) typ 1 max 2 unit
electrical characteristics mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 17 figure 9. typical run i dd vs. bus frequency (v dd = 5v) 10 c lvd adder to stop3 (lvde = lvdse = 1) s3i ddlvd 5 110 180 ? a 3 90 160 ? a 11 c adder to stop3 for oscillator enabled 8 (erefsten =1) s3i ddosc 5,3 5 8 ? a 1 typical values are based on characterization data at 25 ? c. see figure 9 through figure 14 for typical curves across temperature and voltage. 2 max values in this column apply for the full operating temperature range of the device unless otherwise noted. 3 all modules except adc active, ics configured for fbelp, and does not include any dc loads on port pins 4 all modules except adc active, ics configured for fe i, and does not include any dc loads on port pins 5 all modules except adc active, ics configured for fe i, and does not include any dc loads on port pins 6 stop currents are tested in production for 25 ? c on all parts. tests at other temperatures depend upon the part number suffix and maturity of the product. freescale may el iminate a test insertion at a particular temperature from the production test flow once sufficient data has been collected and is approved. 7 most customers are expected to find that auto-wakeup fr om stop2 or stop3 can be used instead of the higher current wait mode. 8 values given under the following conditions: low range o peration (range = 0) with a 32.768khz crystal and low power mode (hgo = 0). table 8. supply current characteristics (continued) num c parameter symbol v dd (v) typ 1 max 2 unit 0 2 4 6 8 10 12 14 16 2 8 16 20 25 fbus (mhz) run idd (ma) fbe fei
mc9s08mp16 series data sheet, rev. 2 electrical characteristics freescale semiconductor 18 figure 10. typical run i dd vs. temperature (v dd = 5v, f bus = 8mhz) figure 11. typical run i dd vs. bus frequency (v dd = 3v) 1 2 3 4 5 6 -40 0 25 85 105 125 temperature (c) run idd (ma) fbe fei 0 2 4 6 8 10 12 14 16 2 8 16 20 25 fbus (mhz) run idd (ma) fbe fei
electrical characteristics mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 19 figure 12. typical run i dd vs. temperature (v dd = 3v, f bus = 8mhz) figure 13. typical stop i dd vs. temperature (v dd = 5v) 1 2 3 4 5 6 -40 0 25 85 105 125 temperature (c) run idd (ma) fbe fei 0 10 20 30 40 50 60 70 -40 25 85 105 125 temperature (c) stop idd (ua) stop2 stop3
mc9s08mp16 series data sheet, rev. 2 electrical characteristics freescale semiconductor 20 figure 14. typical stop i dd vs. temperature (v dd = 3v) 2.8 external oscillator (xosc) characteristics table 9. oscillator electrical specifications num c rating symbol min typ 1 max unit 1c oscillator crystal or resonator (erefs = 1, erclken = 1) low range (range = 0) f lo 32 ? 38.4 khz high range (range = 1) fee 2 or fbe 3 mode f hi 1?16mhz high range (range = 1, hgo = 1) fbelp mode f hi-hgo 1?16mhz high range (range = 1, hgo = 0) fbelp mode f hi-lp 1?8mhz 2? load capacitors c 1, c 2 see crystal or resonator manufacturer?s recommendation. 3? feedback resistor r f m ? low range (32 khz to 100 khz) ? 10 ? high range (1 mhz to 16 mhz) ? 1 ? 4? series resistor r s k ? low range, low gain (range = 0, hgo = 0) ? 0 ? low range, high gain (range = 0, hgo = 1) ? 100 ? high range, low gain (range = 1, hgo = 0) ? 0 ? high range, high gain (range = 1, hgo = 1) ? 8 mhz ? 0 0 ? mhz ? 0 10 ? mhz ? 0 20 0 10 20 30 40 50 60 70 -40 25 85 105 125 temperature (c) stop idd (ua) stop2 stop3
electrical characteristics mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 21 2.9 internal clock source (ics) characteristics 5t crystal start-up time 4 ms low range, low gain (range = 0, hgo = 0) t cstl-lp ? 200 ? low range, high gain (range = 0, hgo = 1) t cstl-hgo ? 400 ? high range, low gain (range = 1, hgo = 0) 5 t csth-lp ?5? high range, high gain (range = 1, hgo = 1) 4 t csth-hgo ?20? 6t square wave input clock fr equency (erefs = 0, erclken = 1) f extal fee mode 2 0.03125 ? 51.34 mhz fbe mode 3 0?51.34mhz fbelp mode 0 ? 51.34 mhz 1 typical data was characterized at 5.0 v, 25 ? c or is recommended value. 2 the input clock source must be divided using rdiv to within the range of 31.25 khz to 39.0625 khz. 3 the input clock source must be divided using rdiv to less than or equal to 39.0625 khz. 4 this parameter is characterized and not te sted on each device. proper pc board layout procedures must be followed to achieve specifications. 5 4 mhz crystal table 10. ics frequency specifications num c characteristic symbol min typ 1 max unit 1a p average internal reference frequency ? factory trimmed (consumer- and industrial-qualified devices) at v dd = 5 v and temperature = 25 ? c f int_t ? 32.768 ? khz 1b p average internal reference frequency ? factory trimmed (automotive-qualified devices) at v dd = 5 v and temperature = 25 ? c f int_t ? 31.25 ? khz 2p internal reference frequency ? user trimmed f int_t 31.25 ? 39.06 khz 3t internal reference start-up time t irefst ? 60 100 ? s table 9. oscillator electrical specifications (continued) num c rating symbol min typ 1 max unit mcu extal xtal crystal or resonator r s c 2 r f c 1
mc9s08mp16 series data sheet, rev. 2 electrical characteristics freescale semiconductor 22 4 p dco output frequency range ? trimmed 2 low range (drs=00) f dco_t 16 ? 20 mhz c mid range (drs=01) 32 ? 40 p high range (drs=10) 48 ? 60 5 p dco output frequency 2 reference = 32768 hz and dmx32 = 1 low range (drs=00) f dco_dmx32 ? 19.92 ? mhz p mid range (drs=01) ? 39.85 ? p high range (drs=10) ? 59.77 ? 6c resolution of trimmed dco output frequency at fixed voltage and temperature (using ftrim) ? f dco_res_t ? ?? 0.1 ?? 0.2 %f dco 7c resolution of trimmed dco output frequency at fixed voltage and temperature (not using ftrim) ? f dco_res_t ? ?? 0.2 ?? 0.4 %f dco 8p total deviation of trimmed dco ou tput frequency over voltage and temperature ? f dco_t ? ?? 0.8 ?? 2 %f dco 9c total deviation of trimmed dco out put frequency over fixed voltage and temperature range of 0 ? c to 70 ? c ? f dco_t ? ?? 0.5 ?? 1 %f dco 10 c fll acquisition time 3 t acquire ?? 1ms 11 c long term jitter of dco output clock (averaged over 2-ms interval) 4 c jitter ? 0.02 0.2 %f dco 1 data in typical column was characterized at 3.0 v, 25 ? c or is typical recommended value. 2 the resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 this specification applies to any time the fll reference source or reference divider is changed, trim value changed or changing from fll disabled (fbelp, fbilp) to fll en abled (fei, fee, fbe, fbi). if a crystal/res onator is being used as the reference, this specification assume s it is already running. 4 jitter is the average deviation from the programmed freq uency measured over the specified interval at maximum f bus . measurements are made with the devi ce powered by filtered supplies and clocked by a stable external clock signal. noise injecte d into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. table 10. ics frequency specifications (continued) num c characteristic symbol min typ 1 max unit
electrical characteristics mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 23 figure 15. typical frequency deviation vs temperature (ics trimmed to 25 mhz bus@25c, 5v, fei) 1 2.10 adc characteristics 1. based on the average of several hundred units from a typical characterization lot. table 11. 12-bit adc operating conditions characteristic conditions symbol min typ 1 1 typical values assume v ddad = 5.0v, temp = 25 ? c, f adck =1.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. max unit comment supply voltage absolute v dda 2.7 ? 5.5 v input voltage v adin v refl ?v refh v input capacitance c adin ?4.55.5pf input resistance r adin ?3 5k ? analog source resistance 12 bit mode f adck > 4mhz f adck < 4mhz r as ? ? ? ? 2 5 k ? external to mcu 10 bit mode f adck > 4mhz f adck < 4mhz ? ? ? ? 5 10 8 bit mode (all valid f adck )??10 adc conversion clock freq. high speed (adlpc=0) f adck 0.4 ? 8.0 mhz low power (adlpc=1) 0.4 ? 4.0 -3% -2% -1% 0% 1% 2% 3% -40-20 0 20406080100120 temperature (c) deviation from trimmed frequency
mc9s08mp16 series data sheet, rev. 2 electrical characteristics freescale semiconductor 24 figure 16. adc input impedance equivalency diagram table 12. 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) c characteristic conditions symb min typ 1 max unit comment t supply current adlpc=1 adlsmp=1 adco=1 i dda ?133? ? a t supply current adlpc=1 adlsmp=0 adco=1 i dda ?218? ? a t supply current adlpc=0 adlsmp=1 adco=1 i dda ?327? ? a t supply current adlpc=0 adlsmp=0 adco=1 i dda ? 0.582 ? ma p adc asynchronous clock source high speed (adlpc=0) f adack 23.35mhzt adack = 1/f adack low power (adlpc=1) 1.25 2 3.3 + ? + ? v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin
electrical characteristics mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 25 d conversion time (including sample time) short sample (adlsmp=0) t adc ? 20 ? adck cycles see adc chapter in the reference manual for conversion time variances long sample (adlsmp=1) ? 40 ? d sample time short sample (adlsmp=0) t ads ? 3.5 ? adck cycles long sample (adlsmp=1) ? 23.5 ? t temp sensor slope -40 ? c to 25 ? c m ? 3.266 ? mv/ ? c 25 ? c to 125 ? c ? 3.638 ? t temp sensor voltage 25 ? cv temp25 ? 1.396 ? mv t total unadjusted error 12 bit mode e tue ? ? 3.0 ? 6.5 lsb 2 includes quantization p 10 bit mode ? ? 1 ? 2.5 t 8 bit mode ? ? 0.5 ? 1.0 t differential non-linearity 12 bit mode dnl ? ? 1.75 ? 3.5 lsb 2 p 10 bit mode 3 ? ? 0.5 ? 1.0 t 8 bit mode 3 ? ? 0.3 ? 0.5 t integral non-linearity 12 bit mode inl ? ? 1.5 ? 4.5 lsb 2 p 10 bit mode ? ? 0.5 ? 1.0 t 8 bit mode ? ? 0.3 ? 0.5 t zero-scale error 12 bit mode e zs ? ? 1.5 0.0/ -3.0 lsb 2 v adin = v ssad p 10 bit mode ? ? 0.5 ? 1.5 t 8 bit mode ? ? 0.5 ? 0.5 t full-scale error 12 bit mode e fs ? ? 1.0 +1.75/ ? 1.25 lsb 2 v adin = v ddad t 10 bit mode ? ? 0.5 ? 1 t 8 bit mode ? ? 0.5 ? 0.5 d quantization error 12 bit mode e q ? -1 to 0 ? lsb 2 10 bit mode ? ? ? 0.5 8 bit mode ? ? ? 0.5 d input leakage error 12 bit mode e il ? ? 1?lsb 2 pad leakage 4 * r as 10 bit mode ? ? 0.2 ? 2.5 8 bit mode ? ? 0.1 ? 1 1 typical values assume v ddad = 5.0v, temp = 25 ? c, f adck =1.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 1 lsb = (v refh - v refl )/2 n 3 monotonicity and no-missing-codes guaranteed in 10 bit and 8 bit modes 4 based on input pad leakage current. refer to pad electricals. table 12. 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) (continued) c characteristic conditions symb min typ 1 max unit comment
mc9s08mp16 series data sheet, rev. 2 electrical characteristics freescale semiconductor 26 2.11 digital to analog (dac) characteristics ? the accuracy at worst case: +/- 1.5% maximum ? the settling time must be less than 100 ns ? when changing the output voltage level, the voltage glitch cannot be completely eliminated 2.12 high speed comparator (hscmp) characteristics 2.13 programmable gain amplifier (pga) characteristics table 13. 5-bit dac characteristics num c characteristic symbol min typical max unit 2 d supply current adder (enabled) i ddac ??20 ? a 3 d dac reference inputs vin v ssa ?v dda v 5 d dac step size v step 0.75 ? v in /32 v in /32 1.25 ? v in /32 v 6 d dac voltage range v dacout v in /32 ? v in v table 14. high speed comparator electrical specifications num c characteristic 1 1 all timing assumes slew rate control disabled and high drive strength enabled. symbol min typical max unit 1 d supply current, high speed mode (en=1, pmode=1) i ddahs ? 200 ? a 2 d supply current, low speed mode (en=1, pmode=0) i ddals ?10 ? a 3 ? analog input voltage v ain v ssa ?v dda v 4 p analog input offset voltage v aio ?540mv 5 c analog comparator hysteresis v h 3.0 9 20.0 mv 6 t propagation delay, high speed mode (en=1, pmode=1) t dhs 2 2 delay from analog input to the cmpxout output pin. measur ed with an input waveform that switches 30 mv above and below the reference. ?70120ns 7 t propagation delay, low speed mode (en=1, pmode=0) t dls 2 ? 400 600 ns 8 d analog comparator initialization delay t ainit ? 400 ? ns table 15. programmable gain amplifier electrical specifications num c parameter symbol min typical max unit 1 t supply current adder ? normal mode (lp=0) ? low power mode (lp=1) i ddon ? ? 450 250 550 300 ua 2 t supply current adder (stand-by) i ddaoff ? 1 10 na 3 t absolute analog input level v il v ssa v dda /2 v dda v
electrical characteristics mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 27 2.14 ac characteristics this section describes timing charact eristics for each peripheral system. 2.14.1 control timing 4 d differential input voltage v diffmax 0 v 5 t linearity (@ voltage gain) 1 ?1x ?2x ?4x ?8x ?16x ?32x l v 1 ? 1/2 lsb 2 ? 1/2 lsb 4 ? 1 lsb 8 ? 1 lsb 16 ? 4 lsb 32 ? 4 lsb 1 2 4 8 16 32 1 + 1/2 lsb 2 + 1/2 lsb 4 + 1 lsb 8 + 1 lsb 16 + 4 lsb 32 + 4 lsb v/v 6 t max gain error e g ?1 2% 7a d pga clock ? normal mode (lp=0) ? low power mode (lp=1) f pga ? ? 8 2 4 8 2 4 mhz 7b d pga sampling frequency 3 f sampl ? ? samples per second 8 d input signal bandwidth bw 0 f sampl ? 8 f sampl ? 2hz 9 d charge pump clock frequency f cpclk 100 f pga ? 4?hz 1 lsb in 12-bit resolution 2 8 mhz is required for pga achieving 1 ? s sampling time. 3 adc in 12-bit mode, long sampling time, f adc =f pga table 16. control timing num c rating symbol min typ 1 max unit 1d bus frequency (t cyc = 1/f bus ) ?40 to 105 ? cf bus dc ? 25.67 mhz ?40 to 125 ? cf bus dc ? 20 mhz 2 p internal low power oscillator period t lpo 700 ? 1300 ? s 3 d external reset pulse width 2 t extrst 100 ? ? ns 4 d reset low drive t rstdrv 34 x t cyc ??ns 5 d bkgd/ms setup time after issuing background debug force reset to enter user or bdm modes t mssu 500 ? ? ns 6 d bkgd/ms hold time after issuing background debug force reset to enter user or bdm modes 3 t msh 100 ? ? ? s table 15. programmable gain amplifier electrical specifications (continued) num c parameter symbol min typical max unit v dda 1.4 ? 2 gain ? ----------------------------- - ? () v dda 1.4 ? 2 gain ? ----------------------------- - 1 12 18 num_clk_gs ? + f pga ------------------------------------------------------------------ ?? ?? 43 f adc ------------- 5 f bus ------------ - ++ ----------------------------------------------------------------------------------------------------
mc9s08mp16 series data sheet, rev. 2 electrical characteristics freescale semiconductor 28 figure 17. reset timing figure 18. kbixpn timing 2.14.2 ftm module timing synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the ftm timer counter. these synchronizers operate from the current icsout clock. the icsout clock period = 0.5 ? t cyc = 1/(f bus ? 2). 7 d keyboard interrupt pulse width asynchronous path 4 synchronous path 5 t ilih, t ihil 100 1.5 x t cyc ? ? ? ? ns 8 c port rise and fall time ? low output drive (ptxds = 0) (load = 50 pf) 6 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall ? ? 40 75 ? ? ns port rise and fall time ? high output drive (ptxds = 1) (load = 50 pf) 6 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall ? ? 11 35 ? ? ns 1 typical values are based on characterization data at v dd = 5.0v, 25 ? c unless otherwise stated. 2 this is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3 to enter bdm mode following a por, bkg d/ms should be held low during the power-up and for a hold time of t msh after v dd rises above v lv d . 4 this is the minimum pulse width that is guaranteed to be recognized as a keyboard interrupt request in stop mode. 5 this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypasse d so shorter pulses can be recognized in that case. 6 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 ? c to 125 ? c. table 17. ftm input timing no. c function symbol min max unit 1 d external clock frequency f tclk 0f icsout /4 1 hz 2 d external clock period t tclk 2?t cyc 3 d external clock high time t clkh 0.75 ? t cyc table 16. control timing (continued) num c rating symbol min typ 1 max unit t extrst reset pin t ihil kbixpn t ilih kbixpn
electrical characteristics mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 29 figure 19. ftm external clock figure 20. ftm input capture pulse 2.14.3 mtim module timing synchronizer circuits determine th e fastest clock that can be used as the opti onal external clock sour ce to the mtim timer counter. these synchronizers operate from the current bus rate clock. figure 21. mtim timer external clock 4 d external clock low time t clkl 0.75 ? t cyc 5 d input capture pulse width t icpw 0.75 ? t cyc 1 the maximum external clock frequency is limited to 10mhz due to input filter characteristics. table 18. mtim input timing no. c function symbol min max unit 1 d external clock frequency f tclk 0f bus /4 hz 2 d external clock period t tclk 4?t cyc 3 d external clock high time t clkh 1.5 ? t cyc 4 d external clock low time t clkl 1.5 ? t cyc table 17. ftm input timing (continued) no. c function symbol min max unit t tclk t clkh t clkl tclk t icpw ftmxchn t icpw ftmxchn t tclk t clkh t clkl tclk
mc9s08mp16 series data sheet, rev. 2 electrical characteristics freescale semiconductor 30 2.14.4 spi table 19 and figure 22 through figure 25 describe the timing requirements for the spi system. table 19. spi electrical characteristics num 1 1 refer to figure 22 through figure 25 . crating 2 2 all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. all timing assumes slew rate control disabled and high drive strength enabled for spi output pins. symbol min max unit 1d cycle time master slave t sck t sck 2 4 4096 ? t cyc t cyc 2d enable lead time master slave t lead t lead ? 1/2 1/2 ? t sck t sck 3d enable lag time master slave t lag t lag ? 1/2 1/2 ? t sck t sck 4d clock (spsck) high time master and slave t sckh 1/2 t sck ? 25 ? ns 5d clock (spsck) low time master and slave t sckl 1/2 t sck ? 25 ? ns 6d data setup time (inputs) master slave t si(m) t si(s) 30 30 ? ? ns ns 7d data hold time (inputs) master slave t hi(m) t hi(s) 30 30 ? ? ns ns 8d access time, slave 3 3 time to data active from high-impedance state. t a 040ns 9d disable time, slave 4 4 hold time to high-impedance state. t dis ?40ns 10 d data setup time (outputs) master slave t so t so ? ? 25 25 ns ns 11 d data hold time (outputs) master slave t ho t ho ?10 ?10 ? ? ns ns 12 d operating frequency master (spife=0) slave (spife=0) master (spife=1) slave (spife=1) f op f bus /4096 dc f bus /4096 dc 8 5 f bus /4 5 6 5 6 5 maximum baud rate must be limited to 8 mhz. 6 maximum baud rate must be limited to 5 mhz due to input filter characteristics. mhz mhz mhz
electrical characteristics mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 31 figure 22. spi master timing (cpha = 0) figure 23. spi master timing (cpha = 1) sck (output) sck (output) miso (input) mosi (output) ss 1 (output) msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (modfen = 1, ssoe = 1). 1 2 3 5 6 7 10 11 5 10 4 4 sck (output) sck (output) miso (input) mosi (output) msb in (2) bit 6 . . . 1 lsb in msb out (2) lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) ss (1) (output) 1. ss output mode (modfen = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. notes: 2 1 3 4 5 6 7 10 11 5 4
mc9s08mp16 series data sheet, rev. 2 electrical characteristics freescale semiconductor 32 figure 24. spi slave timing (cpha = 0) figure 25. spi slave timing (cpha = 1) sck (input) sck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1. not defined but normally msb of character just received 1 2 3 4 6 7 8 9 10 11 5 5 4 sck (input) sck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1. not defined but normally lsb of character just received 1 2 3 4 6 7 8 9 10 11 4 5 5
electrical characteristics mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 33 2.15 flash memory specifications this section provides details about program/erase ti mes and program-erase endurance for the flash memory. program and erase operations do not require any special power sources ot her than the normal v dd supply. for more detailed information about program/erase op erations, see the memory section. 2.16 emc performance electromagnetic compatibility (emc) performance is highly de pendant on the environment in which the mcu resides. board design and layout, circuit topology choices, location and charact eristics of external components as well as mcu software operation all play a significant role in emc performance. the sy stem designer should consult fr eescale applications notes such as an2321, an1050, an1263, an2764, and an1259 for advice and guidance specifically targeted at optimizing emc performance. 2.16.1 radiated emissions microcontroller radiated rf emissions ar e measured from 150 khz to 1 ghz usi ng the tem/gtem cell method in accordance with the iec 61967-2 and sae j1752/3 standards. the measurem ent is performed with the microcontroller installed on a table 20. flash memory characteristics num c characteristic symb ol min typical max unit 1 ? supply voltage for program/erase -40 ? c to 125 ? cv prog/erase 2.7 5.5 v 2 ? supply voltage for read operation v read 2.7 5.5 v 3 ? internal fclk frequency 1 1 the frequency of this clock is controlled by a software setting. f fclk 150 200 khz 4 ? internal fclk period (1/fclk) t fcyc 56.67 ? s 5 c byte program time (random location) 2 t prog 9t fcyc 6 ? byte program time (burst mode) 2 t burst 4t fcyc 7 d page erase time 2 2 these values are hardware state machine controlled. user code does not need to count cycles. this information supplied for calculating approximate time to program and erase. t page 4000 t fcyc 8 d mass erase time 2 t mass 20,000 t fcyc 9 c byte program current 3 3 the program and erase currents are additional to the standard run i dd . these values are measured at room temperatures with v dd = 5.0 v, bus frequency = 4.0 mhz. r iddbp ?4 ?ma 10 c page erase current 3 r iddpe ?6?ma 11 c program/erase endurance 4 t l to t h = ?40 ? c to + 125 ? c t = 25 ? c 4 typical endurance for flash is based upon the intrinsic bit cell performance. for additional information on how freescale defines typical endurance, please refer to engineering bulletin eb619/d, typical endurance for nonvolatile memory . 10,000 ? 100,000 ? ? cycles 12 c data retention 5 5 typical data retention values are based on intrinsic capability of the tec hnology measured at high te mperature and de-rated to 25 ? c using the arrhenius equation. for additional information on how freescale defines typical data retention, please refer to engineering bulletin eb618/d, typical data retention for nonvolatile memory. t d_ret 15 100 ? years
mc9s08mp16 series data sheet, rev. 2 ordering information freescale semiconductor 34 custom emc evaluation board while running specialized emc test software. the radiated emissions from the microcontroller are measured in a tem cell in two pack age orientations (north and east). the maximum radiated rf emissi ons of the tested configuration in all orientations are less than or equal to the reported emissions levels. 3 ordering information this section contains ordering information for mc9s08mp16 and mc9s08mp12 devices. table 21. radiated emissions, electric field parameter symbol conditions frequency f osc /f bus level 1 (max) 1 data based on qualification test results. the reported emission level is the value of the maximum emission, rounded up to the next whole number, from among the measured orientations in each frequency range. unit radiated emissions, electric field v re_tem v dd = 5v ta = +25 ? c package type 48 lqfp 0.15 ? 50 mhz 4 mhz crystal 2 mhz bus 3 db ? v 50 ? 150 mhz 8 150 ? 500 mhz ?4 500 ? 1000 mhz ?8 iec level 2 2 iec level maximums: n ? 12 db ? v, l ? 24 db ? v, i ? 36 db ? v n ? sae level 3 3 sae level maximums: 1 ? 10 db ? v, 2 ? 20 db ? v, 3 ? 30 db ? v, 4 ? 40 db ? v 1 ? table 22. device and package options device number 1 1 see the mc9s08mp16rm reference manual (mc9s08mp16rm) for a complete description of modules included on each device. temp range memory available packages 2 2 see ta bl e 2 3 for package information. flash ram 48-pin 32-pin 28-pin consumer and indust rial qualification mc9s08mp16 v 16k 1024 48 lqfp 32 lqfp 28 soic mc9s08mp12 v 12k 512 ? ? 28 soic automotive qualification s9s08mp16 c, v, m 16k 1024 48 lqfp ? ?
package information mc9s08mp16 series data sheet, rev. 2 freescale semiconductor 35 3.1 device numbering scheme example of the device numbering system: 4 package information the latest package outline drawings are available on the product summary pages on our web site: http://www.freescale.com/8bit . the following table lists the document number s per package. use these numbers in the web page?s keyword search engine to find the latest package outline drawings. note the 32 lqfp and 28 soic are not qualified to meet automotive requirements. 5 related documentation find the most current versions of all documents at http://www.freescale.com . 6 revision history to provide the most up-to-date information, the revision of our documents on the world wide we b are the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www.freescale.com table 23. package descriptions pin count package type abbreviation designator case no. document no. 48 low quad flat pack lqfp lf 932-03 98ash00962a 32 low quad flat pack lqfp lc 873a-03 98ash70029a 28 small outline integrated circuit soic wl 751f-05 98asb42345b reference manual (mc9s08mp16rm) contains extensive product informati on including modes of operation, memory, resets and interrupts, register definition, port pins, cpu, and all module information. xx temperature range family memory status core 9 = flash-based 9s08 zz mc = consumer & package designator (see ta b l e 2 3 ) flash size nn y v = ?40 ? c to 105 ? c s = automotive qualified m = ?40 ? c to 125 ? c mp e2 wafer fab site and mask revision 16 kbytes 12 kbytes (this field appears only in automotive-qualified part numbers) industrial c = ?40 ? c to 85 ? c
document number: mc9s08mp16 rev. 2 08/2011 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2009-2011. all rights reserved. table 24 summarizes changes contained in this document. table 24. revision history rev date description of changes 1 10/15/2009 initial public revision 2 08/09/2011 updated table 10. changed the value of row 8 column ?c? from to c to p.

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